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Logic Synthesis School Kit

Breadboard exercises

Build the circuit. Describe the hardware. Verify the behavior.

SystemVerilog style rules · four-space indentation

BB-FSM-01 · CMOS → RTL → FPGA → ASIC

Timofei’s traffic light

Ten states, three OR functions, three chips. Red for four ticks, yellow for two and green for four. One complete lesson includes pinouts, three schematics, a verified wiring list, SystemVerilog and simulator scripts.

Open the exercise
Traffic-light Moore state diagram