// Generated by tools/build_diagrams.py from the same pins/nets as the drawings.
// Synthesizable with the ideal chip models; all supply pins are physical-only.

module traffic_light_chips
(
    input              clk,
    input              rst,

    output             red,
    output             yellow,
    output             green,
    output       [9:0] state
);

    timeunit 1ns;
    timeprecision 1ps;

    cd4017b u1
    (
        .p3_q0        (state [0]),
        .p2_q1        (state [1]),
        .p4_q2        (state [2]),
        .p7_q3        (state [3]),
        .p10_q4       (state [4]),
        .p1_q5        (state [5]),
        .p5_q6        (state [6]),
        .p6_q7        (state [7]),
        .p9_q8        (state [8]),
        .p11_q9       (state [9]),
        .p12_carry    (),
        .p13_inhibit  (1'b0),
        .p14_clock    (clk),
        .p15_reset    (rst)
    );

    cd4072b u2
    (
        .p1_j         (red),
        .p2_a         (state [0]),
        .p3_b         (state [1]),
        .p4_c         (state [2]),
        .p5_d         (state [3]),
        .p9_e         (state [6]),
        .p10_f        (state [7]),
        .p11_g        (state [8]),
        .p12_h        (state [9]),
        .p13_k        (green)
    );

    cd4071b u3
    (
        .p1_a         (state [4]),
        .p2_b         (state [5]),
        .p3_j         (yellow),
        .p4_k         (),
        .p5_c         (1'b0),
        .p6_d         (1'b0),
        .p8_e         (1'b0),
        .p9_f         (1'b0),
        .p10_l        (),
        .p11_m        (),
        .p12_g        (1'b0),
        .p13_h        (1'b0)
    );

endmodule